module counter(
    input   wire            clk     ,
    input   wire            clear   ,
    input   wire            updown  ,
    input   wire            load    ,
    input   wire    [7:0]   d       ,
    output  reg     [7:0]   q        
);

always @(posedge clk) begin 
    if(clear == 1'b0) begin 
        q <= 8'b0;
    end
    else if(load) begin 
        q <= d;
    end
    else if(updown) begin 
        q <= q + 8'h01;
    end
    else begin // updown == 1'b0
        q <= q - 8'h01;
    end
end

endmodule